Japanese Patent Application No. 2001-221789, filed on Jul. 23, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a nonvolatile semiconductor storage device constructed of memory cells each including two nonvolatile memory elements which are controlled by one word gate and two control gates.
Known as a nonvolatile semiconductor device is the MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or -Substrate) type wherein the gate insulator layer between a channel and a gate is formed of a stacked structure consisting of a silicon oxide film, a silicon nitride film and another silicon oxide film, and wherein electric charges are trapped in the silicon. nitride film.
The MONOS type nonvolatile semiconductor storage device is disclosed in a publication, Y. Hayashi, et al.: 2000 Symposium on VLSI Technology, Digest of Technical Papers, p.122 to p.123. The publication teaches a MONOS flash memory cell including two nonvolatile memory elements (also termed xe2x80x9cMONOS memory elements or cellsxe2x80x9d) which are controlled by one word gate and two control gates. That is, one flash memory cell has two trap sites for charges.
A plurality of MONOS flash memory cells each having such a structure are arranged in each of a row direction and a column direction, thereby to construct a memory cell array region.
Two bit lines, one word line and two control gate lines are required for driving each MONOS flash memory cell. In driving a large number of memory cells, however, such lines can be connected in common in a case where even the different control gates are set at the same potential.
Here, when the control gate line is shared by the large number of memory cells, the load there of enlarges, and the high speed drive of the storage device is impossible. Moreover, the storage device dissipates more electric power and becomes unsuited to portable equipment etc.
These problems can be solved in such a way that the control gate lines are divided into a main control gate line and sub control gate lines, and that only the sub control gate line connected to the memory cell within a block area to-be-selected is connected to the main control gate line through a control gate line selection transistor.
With this method, however, the gate voltage of the control gate line selection transistor must be boosted in order that a voltage to be applied to the control gate line may be ensured especially as in a data read mode.
The present invention may provide a nonvolatile semiconductor storage device in which control voltages to control-gate-line selection switching elements are lowered by analyzing the operation of reading data from memory cells.
The present invention may further provide a nonvolatile semiconductor storage device in which control voltages to control-gate-line selection switching elements are lowered by analyzing the operation of writing data into memory cells.
A nonvolatile semiconductor storage device according to a first aspect of the present invention comprises:
a memory cell array region in which a plurality of memory cells are arranged in a first direction and a second direction intersecting with each other, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates;
a plurality of sub control gate lines which extend in the first direction and are respectively disposed in a plurality of block areas formed by dividing the memory cell array region in the first direction, each of the sub control gate lines being connected with the first nonvolatile memory element of one of two the memory cells adjacent to each other in the second direction and the second nonvolatile memory element of the other of the two memory cells;
a plurality of main control gate lines each of which is formed extending over the block areas arranged in the first direction, and connected in common to corresponding sub control gate lines in each of the block areas arranged in the first direction;
a plurality of control-gate-line selection switching elements which are respectively disposed at connection points between the main control gate lines and the sub control gate lines, and each of the control-gate-line selection switching elements selecting connection or non-connection based on a control voltage; and
a control-gate-line selection driver which supplies the control voltage to the control-gate-line selection switching elements.
Each of the plurality of sub control gate lines is connected to the first control gate of one of two the memory cells adjacent to each other in the second direction, and to the second control gate of the other of the two memory cells.
The plurality of control-gate-line selection switching elements include a first group of control-gate-line selection switching elements and a second group of control-gate-line selection switching elements respectively connected to every second line among the sub control gate lines arranged in the second direction.
The control-gate-line selection driver includes a first control-gate-line selection driver which supplies a first control voltage to the first group of control-gate-line selection switching elements, and a second control-gate-line selection driver which supplies a second control voltage to the second group of control-gate-line selection switching elements.
The first control-gate-lines election driver supplies the first group of control-gate-line selection switching elements with the first control voltage that is set to be higher than the second control voltage when data is read out of one of the first and second nonvolatile memory elements, and the control-gate-line selection switching elements connected to the sub control gate lines to which an override voltage is applied is included in the first group of control-gate-line selection switching elements.
The second control-gate-line selection driver supplies the second group of control-gate-line selection switching elements with the second control voltage that is set to be higher than the first control voltage when data is read out of the other of the first and second nonvolatile memory elements, and the control-gate-line selection switching elements connected to the sub control gate lines to which the override voltage is applied is included in the second group of control-gate-line selection switching elements.
According to the first aspect of the present invention, in a data read mode, only the sub control gate lines selected by the control-gate-line selection switching elements are connected to the main control gate lines, so that the loads of the control gate lines are reduced to permit a high speed operation.
In reading data from a selected cell (selected first or second nonvolatile memory element), the override voltage is set higher in the memory cell including the selected cell. It is therefore necessary to heighten the control voltage of the control-gate-line selection switching element connected with the sub control gate line to which the override voltage is applied.
On the other hand, the read voltage of the memory cell can be set lower as compared with the override voltage. Therefore, the back gate of the control gate line selection transistor connected to the sub control gate line to which the read voltage is applied exerts little influence, and the control voltage of this transistor need not to be made as high as on the side on which the override voltage is applied. In this manner, the control voltage of the control-gate-line selection switching element on one side can be made lower, so that the load of a booster circuit (charge pump) for generating the high voltage can be lightened.
A nonvolatile semiconductor storage device according to a second aspect of the present invention comprises:
a memory cell array region in which a plurality of memory cells are arranged in a first direction and a second direction intersecting with each other, each of the memory cells having first and second nonvolatile memory elements and being controlled by one word gate and first and second control gates;
a plurality of sub control gate lines which extend in the first direction and are respectively disposed in a plurality of block areas formed by dividing the memory cell array region in the first direction, each of the sub control gate lines being connected with the first nonvolatile memory element of one of two the memory cells adjacent to each other in the second direction and the second nonvolatile memory element of the other of the two memory cells;
a plurality of main control gate lines each of which is formed extending over the block areas arranged in the first direction, and connected in common to corresponding sub control gate lines in each of the block areas arranged in the first direction;
a plurality of control-gate-line selection switching elements which are respectively disposed at connection points between the main control gate lines and the sub control gate lines, and each of the control-gate-line selection switching elements selecting connection or non-connection based on a control voltage; and
a control-gate-line selection driver which supplies the control voltage to the control-gate-line selection switching elements.
Each of the plurality of sub control gate lines is connected to the first control gate of one of two the memory cells adjacent to each other in the second direction, and to the second control gate of the other of the two memory cells.
The plurality of control-gate-line selection switching elements include a first group of control-gate-line selection switching elements and a second group of control-gate-line selection switching elements respectively connected to every second line among the sub control gate lines arranged in the second direction.
The control-gate-line selection driver includes a first control-gate-line selection driver which supplies a first control voltage to the first group of control-gate-line selection switching elements, and a second control-gate-line selection driver which supplies a second control voltage to the second group of control-gate-line selection switching elements.
The first control-gate-line selection driver supplies the first group of control-gate-line selection switching elements with the first control voltage that is set to be lower than the second control voltage when data is written into one of the first and second nonvolatile memory elements, and the control-gate-line selection switching elements connected to the sub control gate lines to which an override voltage is applied is included in the first group of control-gate-line selection switching elements.
The second control-gate-line selection driver supplies the second group of control-gate-line selection switching elements with the second control voltage that is set to be lower than the first control voltage when data is written into the other of the first and second nonvolatile memory elements, and the control-gate-line selection switching elements connected to the sub control gate lines to which the override voltage is applied is included in the second group of control-gate-line selection switching elements.
According to the second aspect of the present invention, in a data program mode, only the sub control gate lines selected by the control-gate-line selection switching elements are connected to the main control gate lines, so that the loads of the control gate lines are reduced to permit a high speed operation.
In programming data from a selected cell (selected first or second nonvolatile memory element), the write voltage is set higher in the memory cell including the selected cell. It is therefore necessary to heighten the control voltage of the control-gate-line selection switching element connected with the sub control gate line to which the write voltage is applied.
On the other hand, the override voltage of the memory cell can be set lower than the write voltage. Therefore, the back gate of the control gate line selection transistor connected to the sub control gate line to which the override voltage is applied exerts little influence, and the control voltage of this transistor need not be made so high as on the side on which the write voltage is applied. In this manner, the control voltage of the control-gate-line selection switching element on one side can be made low, so that the load of a booster circuit (charge pump) for generating the high voltage can be lightened.
Each of the nonvolatile semiconductor storage devices according to the first and second aspects of the present invention may be constructed as stated below.
A control-gate-line-selection voltage control circuit which supplies the first and second control voltages to the first and second control-gate-line selection drivers maybe included.
A predecoder which predecodes an address signal for specifying one of the first and second nonvolatile memory elements that is to be selected, may be included. In this case, the control-gate-line-selection voltage control circuit may set each of the first and second control voltages at one of a lower voltage and a higher voltage in accordance with a predecoded output from the predecoder.
Each of the first and second control-gate-line selection drivers may be disposed in respective one of the plurality of block areas arranged in the first direction. In this case, the control-gate-line-selection voltage control circuit may supply the first and second control voltages to the first and second control-gate-line selection drivers, respectively.
A global decoder which collectively selects the block areas arranged in the second direction, based on the predecoded output delivered from the predecoder may be included. In this case, the first and second control-gate-line selection drivers may supply the first and second control voltages to the first and second groups of control-gate-line selection switching elements, respectively, when a decoded output from the global decoder is active.
The first and second control-gate-line selection drivers may respectively be arranged in local driver areas which are adjacent to each of the block areas in the second direction.
In this case, an odd-numbered block area and an even-numbered block area among the block areas arranged in the second direction may be disposed adjacent to each other between two of the local driver areas among the local driver areas arranged in the second direction.
In this case, the first group of control-gate-line selection switching elements and the second groups of control-gate-line selection switching elements may respectively be connected to every second line among the sub control gate lines arranged in the second direction in the odd-numbered block area and the even-numbered block area.
The first control-gate-line selection driver, which drives the first groups of control-gate-line selection switching elements, may be disposed in one of the local driver areas that is adjacent to the odd-numbered block area, and the second control-gate-line selection driver, which drives the second groups of control-gate-line selection switching elements, may be disposed in another of the local driver areas that is adjacent to the even-numbered block area. Thus, the first and second control gate line selection drivers may be shared by the two block areas.
Each of the first and second nonvolatile memory elements may include an ONO film formed of an oxide film (O), a nitride film (N) andanoxide film (O), as a trap site for electric charges. However, this is not restrictive, but another structure can be adopted.